fc5a72cba68d524f35fb42b6d5a9704ad5d55b07
[openwrt/staging/ynezz.git] /
1 From 0094872a5e8e4664c6ea1b2dfa487063d39ae363 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Sun, 24 Mar 2013 19:26:26 +0100
4 Subject: [PATCH] rt2x00: rt2800lib: add MAC register initialization for
5 RT3883
6
7 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
8 ---
9 drivers/net/wireless/ralink/rt2x00/rt2800.h | 14 ++++++++++++++
10 drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 19 ++++++++++++++++---
11 2 files changed, 30 insertions(+), 3 deletions(-)
12
13 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
14 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
15 @@ -1728,6 +1728,20 @@
16 #define TX_PWR_CFG_9B_STBC_MCS7 FIELD32(0x000000ff)
17
18 /*
19 + * TX_TXBF_CFG:
20 + */
21 +#define TX_TXBF_CFG_0 0x138c
22 +#define TX_TXBF_CFG_1 0x13a4
23 +#define TX_TXBF_CFG_2 0x13a8
24 +#define TX_TXBF_CFG_3 0x13ac
25 +
26 +/*
27 + * TX_FBK_CFG_3S:
28 + */
29 +#define TX_FBK_CFG_3S_0 0x13c4
30 +#define TX_FBK_CFG_3S_1 0x13c8
31 +
32 +/*
33 * RX_FILTER_CFG: RX configuration register.
34 */
35 #define RX_FILTER_CFG 0x1400
36 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
37 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
38 @@ -5512,6 +5512,12 @@ static int rt2800_init_registers(struct
39 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
40 0x00000000);
41 }
42 + } else if (rt2x00_rt(rt2x00dev, RT3883)) {
43 + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
44 + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
45 + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
46 + rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
47 + rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
48 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
49 rt2x00_rt(rt2x00dev, RT5392) ||
50 rt2x00_rt(rt2x00dev, RT6352)) {
51 @@ -5725,6 +5731,11 @@ static int rt2800_init_registers(struct
52 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
53 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
54
55 + if (rt2x00_rt(rt2x00dev, RT3883)) {
56 + rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
57 + rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
58 + }
59 +
60 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
61 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
62 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,