drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
authorImre Deak <imre.deak@intel.com>
Wed, 12 Jul 2017 15:54:13 +0000 (18:54 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 27 Jul 2017 07:38:53 +0000 (09:38 +0200)
commit001bd2cb17f7df768fb3a5c1e7c3d2cd2cfb3439
treeb636e86661eae841800d0d4812b8e109068784f5
parent1af474fef2697a1ab7e497627bddf026a3e767ac
drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes

The pattern of a power well backing a set of pipe IRQ or VGA
functionality applies to all HSW+ platforms. Using power well attributes
instead of platform checks to decide whether to init/reset pipe IRQs and
VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
GEN9+ power well code in follow-up patches.

Also use u8 for pipe_mask in related helpers to match the type in the
power well struct.

v2:
- Use u8 instead of u32 for irq_pipe_mask. (Ville)

v3:
- Use u8 for pipe_mask in related helpers too for clarity.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170712155413.29839-1-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_runtime_pm.c