arm64: tlbflush: Ensure start/end of address range are aligned to stride
authorWill Deacon <will.deacon@arm.com>
Tue, 11 Jun 2019 11:47:34 +0000 (12:47 +0100)
committerWill Deacon <will.deacon@arm.com>
Wed, 12 Jun 2019 15:19:45 +0000 (16:19 +0100)
commit01d57485fcdb9f9101a10a18e32d5f8b023cab86
treee59acccd8a79ac64da328eafa2e93f5fb012d74c
parentfa63da2ab046b885a7f70291aafc4e8ce015429b
arm64: tlbflush: Ensure start/end of address range are aligned to stride

Since commit 3d65b6bbc01e ("arm64: tlbi: Set MAX_TLBI_OPS to
PTRS_PER_PTE"), we resort to per-ASID invalidation when attempting to
perform more than PTRS_PER_PTE invalidation instructions in a single
call to __flush_tlb_range(). Whilst this is beneficial, the mmu_gather
code does not ensure that the end address of the range is rounded-up
to the stride when freeing intermediate page tables in pXX_free_tlb(),
which defeats our range checking.

Align the bounds passed into __flush_tlb_range().

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reported-by: Hanjun Guo <guohanjun@huawei.com>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm64/include/asm/tlbflush.h