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(parent: 419c9e9) | patch
tools/power turbostat: Baytrail c-state support
authorLen Brown <len.brown@intel.com>
Fri, 10 Feb 2017 05:27:20 +0000 (00:27 -0500)
committerLen Brown <len.brown@intel.com>
Wed, 1 Mar 2017 05:14:02 +0000 (00:14 -0500)
commit0539ba118fe241b0d03202fda0cd19cb758b7fbd
treef4c62d97e838497c699a33ef0f94aaa4ecccae96tree | snapshot
parent419c9e986ea453d07140bffb9708d730b6317e8ecommit | diff
tools/power turbostat: Baytrail c-state support

The Baytrail SOC, with its Silvermont core, has some unique properties:

1. a hardware CC1 residency counter
2. a module-c6 residency counter
3. a package-c6 counter at traditional package-c7 counter address.

The SOC does not support c3, pc3, c7 or pc7 counters.

Signed-off-by: Len Brown <len.brown@intel.com>
arch/x86/include/asm/msr-index.h diff | blob | history
tools/power/x86/turbostat/turbostat.c diff | blob | history
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