drm/amd/display: always use 4 dp lanes for dml
authorJun Lei <Jun.Lei@amd.com>
Fri, 3 May 2019 19:59:54 +0000 (15:59 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Sat, 22 Jun 2019 14:34:12 +0000 (09:34 -0500)
commit1621f4c417bf31e2b741a3d876b1d61435a41e18
tree3c8c5a44c130e8e2f1d8c9f03988a4cad0bb2fe6
parent278141f58e2c9c8f7830f40086c1d43edc6c268b
drm/amd/display: always use 4 dp lanes for dml

[why]
current DML logic uses currently trained setting for number
of dp lanes in DML calculations.  this is obviously flawed since
just because 1 lane is in use doesn't mean only 1 lane can be used

this causes mode validation to fail depending on current state,
which is incorrect

[how]
DML should always assume 4 lanes are available.  validation of
bandwidth is not supposed to be handled by DML, since we do
link validation without DML already

also, DML is expecting there to be a copy of the max state, this
state is removed when update_bounding_box is called to update
actual SKU clocks.  fix this as well by duping last state.

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Eric Yang <eric.yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c