riscv64: add new port on 5.10
authorZoltan HERPAI <wigyori@uid0.hu>
Sun, 16 Dec 2018 10:05:58 +0000 (11:05 +0100)
committerZoltan HERPAI <wigyori@uid0.hu>
Sun, 24 Jan 2021 23:07:45 +0000 (00:07 +0100)
commit2148a50a874206c2914bb9efe8ccbff58b94e5ca
tree1af14f30e23f66550c6d20cf4765a1980458981b
parentdf7fcf154bee9a4445183d36fb67d04ea01d00d0
riscv64: add new port on 5.10

RISC-V is a new CPU architecture aimed to be fully free and open. This
target will add support for it, based on 4.19.

Supports running on:
 - HiFive Unleashed (which is the most known devboard for this arch)
 - QEMU (support is available in mainline qemu)
Further devboards are expected given the interest in this new arch.

An SD-card image is generated, where the partitions are required to have
specific type codes. Compared to earlier branches for this target, BBL
support is removed, giving way for OpenSBI.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
target/linux/riscv64/Makefile [new file with mode: 0644]
target/linux/riscv64/base-files/etc/board.d/02_network [new file with mode: 0644]
target/linux/riscv64/base-files/etc/inittab [new file with mode: 0644]
target/linux/riscv64/base-files/lib/preinit/80_debug [new file with mode: 0644]
target/linux/riscv64/config-5.10 [new file with mode: 0644]
target/linux/riscv64/image/Config.in [new file with mode: 0644]
target/linux/riscv64/image/Makefile [new file with mode: 0644]
target/linux/riscv64/image/gen_riscv64_sdcard_img.sh [new file with mode: 0755]