drm/i915/icl: Define register for DSI PLL
authorMadhav Chauhan <madhav.chauhan@intel.com>
Thu, 5 Jul 2018 13:01:48 +0000 (18:31 +0530)
committerJani Nikula <jani.nikula@intel.com>
Thu, 5 Jul 2018 13:27:56 +0000 (16:27 +0300)
commit27efd2566cb89b7909366dbb88add8fb1e3d24e2
treeaff783880ce68ba7feb9b1607ade8fcc33f47454
parent0f17d5dd2199555830482b638a5fc8bf915f2f10
drm/i915/icl: Define register for DSI PLL

This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.

v2: Review comments from Jani N
    - Fix spaces while defining ICL_ESC_CLK_DIV_MASK
    - Define shift and mask for bitfields.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530795727-28644-2-git-send-email-madhav.chauhan@intel.com
drivers/gpu/drm/i915/i915_reg.h