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(parent: 574f4e8) | patch
clk: ingenic: Add missing flag for UDC clock
authorPaul Cercueil <paul@crapouillou.net>
Wed, 27 Jun 2018 12:14:59 +0000 (14:14 +0200)
committerStephen Boyd <sboyd@kernel.org>
Fri, 6 Jul 2018 18:47:28 +0000 (11:47 -0700)
commit2b555a4b9caecfcab1b2aade176df795ceceaefa
tree669673479270703249ca63368e52ea548a6eb7f6tree | snapshot
parent574f4e80d59e5c669c0729718525df8bac5e4d78commit | diff
clk: ingenic: Add missing flag for UDC clock

The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/jz4740-cgu.c diff | blob | history
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