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(parent: e779fc9) | patch
powerpc/64s: Fix data interrupts vs d-side MCE reentrancy
authorNicholas Piggin <npiggin@gmail.com>
Tue, 26 Feb 2019 08:51:10 +0000 (18:51 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Tue, 26 Feb 2019 12:28:26 +0000 (23:28 +1100)
commit38555434a910a657ba6d7d06a4fe0376c8b04685
treecd1b893915eff74c542d57bc3187e59bebdf22cbtree | snapshot
parente779fc93643c1181b0164745a537986a525850cacommit | diff
powerpc/64s: Fix data interrupts vs d-side MCE reentrancy

Handlers for interrupts that set DAR / DSISR, set MSR[RI] before those
SPRs are read. If a d-side machine check hits in this window, DAR /
DSISR will be clobbered silently, leading to random corruption.

Fix this by having handlers save those registers before setting MSR[RI].

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/kernel/exceptions-64s.S diff | blob | history
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