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(parent: 1ec7032) | patch
clk: tegra: Use correct parent for dpaux clock
authorThierry Reding <treding@nvidia.com>
Mon, 20 Apr 2015 12:47:25 +0000 (14:47 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 28 Apr 2016 10:41:48 +0000 (12:41 +0200)
commit3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707
tree0cfdef423920ea986eaa0bec6d8892ec741bc0cetree | snapshot
parent1ec7032ad517714108cc53a6ee7067276ca21e80commit | diff
clk: tegra: Use correct parent for dpaux clock

The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra-periph.c diff | blob | history
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