projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ce397d2) | patch
clk: renesas: r8a7795: Add CR clock
authorGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 17 May 2018 09:04:15 +0000 (11:04 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 19 Jun 2018 08:19:51 +0000 (10:19 +0200)
commit3d5155eaadaf512808cb57ec0c7db7bd4cc1ef67
treeb552e62b9222acd545013611a84241122220d836tree | snapshot
parentce397d215ccd07b8ae3f71db689aedb85d56ab40commit | diff
clk: renesas: r8a7795: Add CR clock

Add the CR core clock, which is used by the Secure Engine (SCEG).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Tested-by: Gilad Ben-Yossef <gilad@benyossef.com>
drivers/clk/renesas/r8a7795-cpg-mssr.c diff | blob | history
John Crispins staging tree