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(parent: 52ca14e) | patch
drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE
authorChangbin Du <changbin.du@intel.com>
Tue, 15 May 2018 02:35:36 +0000 (10:35 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Mon, 9 Jul 2018 02:23:04 +0000 (10:23 +0800)
commit40b271767dcf9748327619ed550be810cc2e10ae
tree08df1e5c0e9e52a0fc56b307728d835554c60f25tree | snapshot
parent52ca14e6844a04e174b5cd3d7dbf63a23271775ccommit | diff
drm/i915/gvt: Detect 64K gtt entry by IPS bit of PDE

This change help us detect the real entry type per PSE and IPS setting.
For 64K entry, we also need to check reg GEN8_GAMW_ECO_DEV_RW_IA.

v2: Extend IPS mmio control to Gen10. (Matthew Auld)

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/gtt.c diff | blob | history
drivers/gpu/drm/i915/gvt/gtt.h diff | blob | history
John Crispins staging tree