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(parent: b263401) | patch
drm/i915: panel power sequencing for VLV eDP v2
authorJesse Barnes <jbarnes@virtuousgeek.org>
Thu, 28 Mar 2013 16:55:41 +0000 (09:55 -0700)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 2 Apr 2013 18:54:31 +0000 (20:54 +0200)
commit453c542059cfa1988cabcf84f715307cd9789163
tree5d6019f071131d1e4f8e7953e62918f4127c622ftree | snapshot
parentb2634017b2df5e45567811b5e82eb0c8ce8e5ebdcommit | diff
drm/i915: panel power sequencing for VLV eDP v2

PPS register offsets have changed in Valleyview.

v2: don't clobber port select bits on VLV when fixing up PPS timings
    don't bother with G4x PPS regs (Jani)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
drivers/gpu/drm/i915/intel_dp.c diff | blob | history
John Crispins staging tree