x86/tsc: Force inlining of cyc2ns bits
authorPeter Zijlstra <peterz@infradead.org>
Thu, 11 Oct 2018 10:38:26 +0000 (12:38 +0200)
committerThomas Gleixner <tglx@linutronix.de>
Sun, 14 Oct 2018 09:11:22 +0000 (11:11 +0200)
commit4907c68abd3f60f650f98d5a69d4ec77c0bde44f
tree1a08e7f0fab0e26c4d8651598bb7450c8e3faeed
parent3a27203102ebfa67bd0bced05b1def499bb59db2
x86/tsc: Force inlining of cyc2ns bits

Looking at the asm for native_sched_clock() I noticed we don't inline
enough. Mostly caused by sharing code with cyc2ns_read_begin(), which
we didn't used to do. So mark all that __force_inline to make it DTRT.

Fixes: 59eaef78bfea ("x86/tsc: Remodel cyc2ns to use seqcount_latch()")
Reported-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: hpa@zytor.com
Cc: eric.dumazet@gmail.com
Cc: bp@alien8.de
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20181011104019.695196158@infradead.org
arch/x86/kernel/tsc.c