drm/i915: Only set gem object L3 cache level for IVB devices
authorWayne Boyer <wayne.boyer@intel.com>
Tue, 8 Dec 2015 17:38:52 +0000 (09:38 -0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 10 Dec 2015 10:07:30 +0000 (11:07 +0100)
commit4d3e904ceb46bc91d68a47be930514b383227a87
tree9fd7a4c43dc39b604cdae14064df4c48bb65fc5a
parentbf6ce93a73c0d70d0d524bc0bb59c5ae80088ea7
drm/i915: Only set gem object L3 cache level for IVB devices

Do some further clean up based on the initial review of
drm/i915: Separate cherryview from valleyview.

In this case, in i915_gem_alloc_context_obj() only call
i915_gem_object_set_cache_level() for Ivy Bridge devices
since later platforms don't have L3 control bits in the PTE.

v2: Expand comment to mention snooping requirement. (Ville, Imre)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Wayne Boyer <wayne.boyer@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449596332-23470-1-git-send-email-wayne.boyer@intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
drivers/gpu/drm/i915/i915_gem_context.c