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(parent: 60cf09e) | patch
clk: rockchip: Add 1.6GHz PLL rate for rk3399
authorDerek Basehore <dbasehore@chromium.org>
Tue, 13 Mar 2018 20:37:19 +0000 (13:37 -0700)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 13 Mar 2018 23:37:22 +0000 (00:37 +0100)
commit4ee3fd4abeca30d530fe67972f1964f7454259d6
tree466579a6610cb0f25a0b836c27dad771367c36aatree | snapshot
parent60cf09e45fbcbbbb3162f02e0923a25ae7f5627ecommit | diff
clk: rockchip: Add 1.6GHz PLL rate for rk3399

We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3399.c diff | blob | history
John Crispins staging tree