net/mlx5e: Replace PTP clock lock from RW lock to seq lock
authorShay Agroskin <shayag@mellanox.com>
Tue, 5 Jun 2018 06:22:18 +0000 (09:22 +0300)
committerSaeed Mahameed <saeedm@mellanox.com>
Thu, 6 Sep 2018 04:14:57 +0000 (21:14 -0700)
commit64109f1dc41f25f4a9c6b114e04b6266bf4128ad
treede38f98480af0b34b5fd01e0c81a182169cdfed5
parent1462e48db0597a3dec8e73d64f3a001936ec398e
net/mlx5e: Replace PTP clock lock from RW lock to seq lock

Changed "priv.clock.lock" lock from 'rw_lock' to 'seq_lock'
in order to improve packet rate performance.

Tested on Intel(R) Xeon(R) CPU E5-2660 v2 @ 2.20GHz.
Sent 64b packets between two peers connected by ConnectX-5,
and measured packet rate for the receiver in three modes:
no time-stamping (base rate)
time-stamping using rw_lock (old lock) for critical region
time-stamping using seq_lock (new lock) for critical region
Only the receiver time stamped its packets.

The measured packet rate improvements are:

Single flow (multiple TX rings to single RX ring):
without timestamping:   4.26 (M packets)/sec
with rw-lock (old lock):  4.1  (M packets)/sec
with seq-lock (new lock): 4.16 (M packets)/sec
1.46% improvement

Multiple flows (multiple TX rings to six RX rings):
without timestamping:    22   (M packets)/sec
with rw-lock (old lock):  11.7 (M packets)/sec
with seq-lock (new lock): 21.3 (M packets)/sec
82.05% improvement

The packet rate improvement is due to the lack of atomic operations
for the 'readers' by the seq-lock.
Since there are much more 'readers' than 'writers' contention
on this lock, almost all atomic operations are saved.
this results in a dramatic decrease in overall
cache misses.

Signed-off-by: Shay Agroskin <shayag@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h
include/linux/mlx5/driver.h