projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 5db40d7) | patch
ARM: dts: r8a77470: Initial SoC device tree
authorBiju Das <biju.das@bp.renesas.com>
Tue, 3 Apr 2018 11:19:38 +0000 (12:19 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Mon, 16 Apr 2018 14:01:55 +0000 (16:01 +0200)
commit6929dfc5918049272e07653b1760b0b305f098e6
tree04699aa424e934f5f4686703a2088e941572299etree | snapshot
parent5db40d7b26d30ac8b7c21313afe03d678cfffaa9commit | diff
ARM: dts: r8a77470: Initial SoC device tree

The initial R8A77470 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a77470.dtsi [new file with mode: 0644] blob
John Crispins staging tree