projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: bec2e6a) | patch
RISC-V: implement low-level interrupt handling
authorChristoph Hellwig <hch@lst.de>
Sat, 4 Aug 2018 08:23:16 +0000 (10:23 +0200)
committerPalmer Dabbelt <palmer@sifive.com>
Mon, 13 Aug 2018 15:31:31 +0000 (08:31 -0700)
commit6ea0f26a7913b2a72f9cbe84e77ad2cbeaaa9dde
treedc077f5075634c43587aa2658247e37b4004e59dtree | snapshot
parentbec2e6ac353d5c8a47c6eea639136bac3990093ecommit | diff
RISC-V: implement low-level interrupt handling

Add support for a routine that dispatches exceptions with the interrupt
flags set to either the IPI or irqdomain code (and the clock source in the
future).

Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/entry.S diff | blob | history
arch/riscv/kernel/irq.c diff | blob | history
John Crispins staging tree