arm64: mm: Ensure writes to swapper are ordered wrt subsequent cache maintenance
authorWill Deacon <will.deacon@arm.com>
Fri, 22 Jun 2018 15:23:45 +0000 (16:23 +0100)
committerCatalin Marinas <catalin.marinas@arm.com>
Fri, 22 Jun 2018 16:23:40 +0000 (17:23 +0100)
commit71c8fc0c96abf8e53e74ed4d891d671e585f9076
tree6cfd0c5ee88a4947614083dc02adc8d7aaedccf1
parentb5b7dd647f2d21b93f734ce890671cd908e69b0a
arm64: mm: Ensure writes to swapper are ordered wrt subsequent cache maintenance

When rewriting swapper using nG mappings, we must performance cache
maintenance around each page table access in order to avoid coherency
problems with the host's cacheable alias under KVM. To ensure correct
ordering of the maintenance with respect to Device memory accesses made
with the Stage-1 MMU disabled, DMBs need to be added between the
maintenance and the corresponding memory access.

This patch adds a missing DMB between writing a new page table entry and
performing a clean+invalidate on the same line.

Fixes: f992b4dfd58b ("arm64: kpti: Add ->enable callback to remap swapper using nG mappings")
Cc: <stable@vger.kernel.org> # 4.16.x-
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
arch/arm64/mm/proc.S