ASoC: tas2552: Correct PDM configuration register bit definitions

ASoC: tas2552: Correct PDM configuration register bit definitions

The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.

The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>