drm/i915/icl: Define DSI timeout registers
authorMadhav Chauhan <madhav.chauhan@intel.com>
Tue, 30 Oct 2018 11:56:21 +0000 (13:56 +0200)
committerJani Nikula <jani.nikula@intel.com>
Wed, 31 Oct 2018 11:16:26 +0000 (13:16 +0200)
commit8bffd204ded8dd52091afe6455104166c0edfed7
treecb932f0492dfc95718ab2fdc14cd236446462efe
parent0f0fe8497d968fef969c16f5dcff7062e85fb409
drm/i915/icl: Define DSI timeout registers

This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
and DSI_TA_TO registers for DSI transcoders '0' and '1'.
They are used for contention recovery on DPHY.

v2: Define SHIFT for bitfields.

v3 by Jani:
- Fix timeout bit definitions

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0b943c028a05edfd61c511d712c65c7e8bf70211.1540900289.git.jani.nikula@intel.com
drivers/gpu/drm/i915/i915_reg.h