hisi_sas: add v2 hw init

hisi_sas: add v2 hw init

Add code to initialise the hardware.

Support is also added to deal with the "am-max-transmissions" (amt)
limitation in hip06 controller #1. This is how many connection requests
we can send on the system bus before waiting for a response.  Due to
chip bus design, controller #1 is limited to 32 amt, while, by design, a
controller supports 64.  The default value for the nibbles in the
relevant registers is 0x40; these need to be programmed with 0x20.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>