drm/i915/dp: Configure Display stream splitter registers during DSC enable
authorManasi Navare <manasi.d.navare@intel.com>
Wed, 28 Nov 2018 20:26:22 +0000 (12:26 -0800)
committerManasi Navare <manasi.d.navare@intel.com>
Thu, 29 Nov 2018 20:30:50 +0000 (12:30 -0800)
commita311b0b5d2094029dce2369d686044131e19e006
tree63d1cb6981d09b8e085bf3f9624840d7e6524cf7
parent5b1ea77228f913df20a445512bd57ea481905d4e
drm/i915/dp: Configure Display stream splitter registers during DSC enable

Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.

v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-11-manasi.d.navare@intel.com
drivers/gpu/drm/i915/intel_vdsc.c