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drm/i915: Fix CHV DSI PLL refclk during state readout
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 15 Mar 2016 14:40:05 +0000 (16:40 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 12 Apr 2016 18:12:02 +0000 (21:12 +0300)
commitae9ec62bdadc4cd3bf893d6baced80aa3a5dbbd6
tree97329e1675016aa44a43ebb7eccbb378ff473e35tree | snapshot
parentf00b56896ec2443a33277f5411de0cbd13071ceccommit | diff
drm/i915: Fix CHV DSI PLL refclk during state readout

Use the proper refclock frequency (100MHz) when reading out the
current DSI clock on CHV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-13-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_dsi_pll.c diff | blob | history
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