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author	David Ahern <david.ahern@oracle.com>
	Thu, 19 Mar 2015 20:06:37 +0000 (16:06 -0400)
committer	David S. Miller <davem@davemloft.net>
	Fri, 20 Mar 2015 01:54:49 +0000 (18:54 -0700)
commit	b5aff55d89c27aedcae9521155b81b6aebb6c5d8
tree	bc59ebea2c767a7d1411441374aa22073f700be5	tree \| snapshot
parent	d51291cb8f32bfae6b331e1838651f3ddefa73a5	commit \| diff

sparc: perf: Add support M7 processor

The M7 processor has a different hypervisor group id and different PCR fast
trap values. PIC read/write functions and PCR bit fields are the same as
the T4 so those are reused.

Signed-off-by: David Ahern <david.ahern@oracle.com>
Acked-by: Bob Picco <bob.picco@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

John Crispins staging tree

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arch/sparc/include/asm/hypervisor.h		diff \| blob \| history
arch/sparc/kernel/hvapi.c		diff \| blob \| history
arch/sparc/kernel/hvcalls.S		diff \| blob \| history
arch/sparc/kernel/pcr.c		diff \| blob \| history
arch/sparc/kernel/perf_event.c		diff \| blob \| history