projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b2ccfdf) | patch
drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver
authorAbhinav Kumar <abhinavk@codeaurora.org>
Thu, 11 Oct 2018 17:18:57 +0000 (10:18 -0700)
committerRob Clark <robdclark@gmail.com>
Tue, 11 Dec 2018 18:07:07 +0000 (13:07 -0500)
commitc1866d44d149a1ea5c303632114fb6aa08cfd263
treea1e06dfb094b565f957434571eb7a2ca826fc7cftree | snapshot
parentb2ccfdf1dde588d0e90d6d235b9ae557cbea5d4dcommit | diff
drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver

Fix the dsi clock names in the DSI 10nm PLL driver to
match the names in the dispcc driver as those are
according to the clock plan of the chipset.

Changes in v2:
- Update the clock diagram with the new clock name

Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c diff | blob | history
John Crispins staging tree