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MIPS: lantiq: timer irq can be different to 7
authorJohn Crispin <blogic@openwrt.org>
Thu, 16 Aug 2012 08:09:20 +0000 (08:09 +0000)
committerJohn Crispin <blogic@openwrt.org>
Wed, 22 Aug 2012 22:08:17 +0000 (00:08 +0200)
commitc2c9c788b91218bccbb9ac31539ffa577fe502bf
treec2e273e08a8c567d7f3909921e581451dcf313f7tree | snapshot
parent61fa969f27ec58296544bf94d058f3aa704cb8d9commit | diff
MIPS: lantiq: timer irq can be different to 7

The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq
code to be able to handle this.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4229/
arch/mips/lantiq/irq.c diff | blob | history
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