clk: stm32mp1: add PLL clocks
authorGabriel Fernandez <gabriel.fernandez@st.com>
Thu, 8 Mar 2018 16:53:58 +0000 (17:53 +0100)
committerMichael Turquette <mturquette@baylibre.com>
Sun, 11 Mar 2018 22:40:33 +0000 (15:40 -0700)
commitc6cf4d3248980c5e1998ce21f3c2d86502f7e1a9
tree29720b145816929e73d9e32a3e2f3aef535a1b73
parentdc32eaac4926b02fddba3ff02030827429394ad7
clk: stm32mp1: add PLL clocks

STMP32MP1 has 4 PLLs.
PLL supports integer and fractional mode.
Each PLL has 3 output dividers (p, q, r)

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
drivers/clk/clk-stm32mp1.c