drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain
authorImre Deak <imre.deak@intel.com>
Thu, 1 Nov 2018 14:04:26 +0000 (16:04 +0200)
committerImre Deak <imre.deak@intel.com>
Thu, 1 Nov 2018 23:24:03 +0000 (01:24 +0200)
commitc7375d9542f121049ff90562c5828e5843747c9a
treed6f7fbf2c5ec18a820b120ec7f72c64b2f078ff6
parent8e4a3ad9b81b7b595676c5fa88cd44a1b788be2e
drm/i915: Configure AUX_CH_CTL when enabling the AUX power domain

Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
parameters. As opposed to this the flag specifying the thunderbolt vs.
non-thunderbolt mode of the port is not related to AUX transfers at all
(rather it's repurposed to enable either TBT or non-TBT PHY HW blocks).
The programming has to be done before enabling the corresponding AUX
power well, so make it part of the power well code.

v3:
- Use existing enable/disable helpers instead of opencoding. (Jose)
- Fix type of is_tc_tbt to remain a bitfield. (Lucas)
- Add comment describing the is_tc_tbt power well flag. (Lucas)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108548
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181101140427.31026-8-imre.deak@intel.com
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_runtime_pm.c