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(parent: 746da42) | patch
mlxsw: reg: Add QoS ReWrite Enable Register
authorPetr Machata <petrm@mellanox.com>
Fri, 27 Jul 2018 12:26:59 +0000 (15:26 +0300)
committerDavid S. Miller <davem@davemloft.net>
Fri, 27 Jul 2018 20:17:50 +0000 (13:17 -0700)
commite67131d9b861eb753b077961e291fc21a59daa28
tree0560c7131bb24b1a202df3d36d41e85e28a30da2tree | snapshot
parent746da42a1f60728fc0f3ba7818ffe8d1aa69cacdcommit | diff
mlxsw: reg: Add QoS ReWrite Enable Register

This register configures the rewrite enable (whether PCP or DSCP value
in packet should be updated according to packet priority) per receive
port.

Signed-off-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlxsw/reg.h diff | blob | history
John Crispins staging tree