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(parent: 2dcabf0) | patch
clk: tegra20: Correct PLL_C_OUT1 setup
authorDmitry Osipenko <digetx@gmail.com>
Wed, 10 Jan 2018 13:59:43 +0000 (16:59 +0300)
committerThierry Reding <treding@nvidia.com>
Mon, 12 Mar 2018 12:59:05 +0000 (13:59 +0100)
commitea141d5819db989eb688cee2713b664faba4f1ca
treea36e14e7a9f6834d33a7e8f97bd9aa756aa10457tree | snapshot
parent2dcabf053c6ecde46f7aa3612c5a57fb8bd185c4commit | diff
clk: tegra20: Correct PLL_C_OUT1 setup

PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's
set it to 240 MHz and explicitly specify HCLK rate for consistency.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra20.c diff | blob | history
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