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author	Thierry Reding <treding@nvidia.com>
	Mon, 20 Apr 2015 13:10:43 +0000 (15:10 +0200)
committer	Thierry Reding <treding@nvidia.com>
	Thu, 28 Apr 2016 10:41:49 +0000 (12:41 +0200)
commit	eede7113aabd3f40f8d9c32b1690f2859fcb101a
tree	ffa6885caeb0e7e1a1e1a64161a4082771cceedc	tree \| snapshot
parent	98c4b3661b5aee0e583d17d6304f6489c0f41155	commit \| diff

clk: tegra: dpaux and dpaux1 are fixed factor clocks

The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.

Signed-off-by: Thierry Reding <treding@nvidia.com>

drivers/clk/tegra/clk-tegra-periph.c		diff \| blob \| history
drivers/clk/tegra/clk-tegra124.c		diff \| blob \| history
drivers/clk/tegra/clk-tegra210.c		diff \| blob \| history

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