projects / openwrt / staging / blogic.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: b85e1f7) | patch
arm64: dts: renesas: initial R8A77980 SoC device tree
authorSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Fri, 2 Feb 2018 18:33:39 +0000 (21:33 +0300)
committerSimon Horman <horms+renesas@verge.net.au>
Mon, 12 Feb 2018 12:52:08 +0000 (13:52 +0100)
commitf3a54d6c17f5ec826ff81e4f9f35a11e63211c53
treee0c4fabe957d47c7b026ccee0de5ac9382c0f96dtree | snapshot
parentb85e1f77d9e285e61f8aa5a3a7e2bc46431d07eecommit | diff
arm64: dts: renesas: initial R8A77980 SoC device tree

The initial R8A77980 SoC device tree including Cortex-A53 CPU, GIC, timer,
CPG, RST, and SYSC.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a77980.dtsi [new file with mode: 0644] blob
John Crispins staging tree