projects / openwrt / staging / wigyori.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4d49ec4) | patch
riscv64: add new port on 5.10 kitchensink-202012
authorZoltan HERPAI <wigyori@uid0.hu>
Sun, 16 Dec 2018 10:05:58 +0000 (11:05 +0100)
committerZoltan HERPAI <wigyori@uid0.hu>
Mon, 21 Dec 2020 09:17:40 +0000 (10:17 +0100)
commit4175a56ccfc292be668e477a83bfdb95624eac93
treefbb09406659428085339ce7a5bb7a38d200b80d1tree | snapshot
parent4d49ec498306b0384bbc4663f360085d9ce04f16commit | diff
riscv64: add new port on 5.10

RISC-V is a new CPU architecture aimed to be fully free and open. This
target will add support for it, based on 4.19.

Supports running on:
 - HiFive Unleashed (which is the most known devboard for this arch)
 - QEMU (support is available in mainline qemu)
Further devboards are expected given the interest in this new arch.

An SD-card image is generated, where the partitions are required to have
specific type codes. Compared to earlier branches for this target, BBL
support is removed, giving way for OpenSBI.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
target/linux/riscv64/Makefile [new file with mode: 0644] blob
target/linux/riscv64/base-files/etc/board.d/02_network [new file with mode: 0644] blob
target/linux/riscv64/base-files/etc/inittab [new file with mode: 0644] blob
target/linux/riscv64/base-files/lib/preinit/80_debug [new file with mode: 0644] blob
target/linux/riscv64/config-5.10 [new file with mode: 0644] blob
target/linux/riscv64/image/Config.in [new file with mode: 0644] blob
target/linux/riscv64/image/Makefile [new file with mode: 0644] blob
target/linux/riscv64/image/gen_riscv64_sdcard_img.sh [new file with mode: 0755] blob
Staging tree of Zoltan Herpai