drm/i915/bxt, glk: Avoid long atomic poll during CDCLK change

There is no requirement for doing the PCODE request polling atomically,
so do that only for a short time switching to sleeping poll afterwards.
The specification requires a 150usec timeout for the change notification,
so let's use that for the atomic poll. Do the extra 2ms poll - needed as
a workaround on BXT/GLK - in sleeping mode.

v2:
- rebase on v2 of patchset dropping the sandybridge_pcode_read/write
  refactoring (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180130142939.17983-2-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8cd4d6f3a160477feb767a08cc9d3de8a455b638..c67385ed0f663e15352e184cf3f78badd5273d1b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3729,9 +3729,10 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
 
 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
-                                   u32 val, int timeout_us);
+                                   u32 val, int fast_timeout_us,
+                                   int slow_timeout_ms);
 #define sandybridge_pcode_write(dev_priv, mbox, val)   \
-       sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500)
+       sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
 
 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
                      u32 reply_mask, u32 reply, int timeout_base_ms);

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index a423b674fcec19e35165b4593f98c50ffc4ee52f..ee788d5be5e36b22bf4af1c9787410315c0fb94f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1378,7 +1378,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
        mutex_lock(&dev_priv->pcu_lock);
        ret = sandybridge_pcode_write_timeout(dev_priv,
                                              HSW_PCODE_DE_WRITE_FREQ_REQ,
-                                             0x80000000, 2000);
+                                             0x80000000, 150, 2);
        mutex_unlock(&dev_priv->pcu_lock);
 
        if (ret) {
@@ -1417,7 +1417,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
         */
        ret = sandybridge_pcode_write_timeout(dev_priv,
                                              HSW_PCODE_DE_WRITE_FREQ_REQ,
-                                             cdclk_state->voltage_level, 2000);
+                                             cdclk_state->voltage_level, 150, 2);
        mutex_unlock(&dev_priv->pcu_lock);
 
        if (ret) {

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3cc2e6fdd98adb9894843f7d73ecca9aa7d18c1e..eb68abf6a8e96727f916129406870ea01772af6a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9215,7 +9215,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
 }
 
 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
-                                   u32 mbox, u32 val, int timeout_us)
+                                   u32 mbox, u32 val,
+                                   int fast_timeout_us, int slow_timeout_ms)
 {
        int status;
 
@@ -9238,7 +9239,8 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
 
        if (__intel_wait_for_register_fw(dev_priv,
                                         GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
-                                        timeout_us, 0, NULL)) {
+                                        fast_timeout_us, slow_timeout_ms,
+                                        NULL)) {
                DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
                          val, mbox, __builtin_return_address(0));
                return -ETIMEDOUT;