drm/i915/psr: Enable CRC check in the static frame on the sink side

Sink can be configured to calculate the CRC over the static frame and
compare with the CRC calculated and transmited in the VSC SDP by
source, if there is a mismatch sink will do a short pulse in HPD
and set DP_PSR_LINK_CRC_ERROR in DP_PSR_ERROR_STATUS.

Spec: 7723

v6:
andling DP_PSR_LINK_CRC_ERROR here and remove "bdw+" from commit
message

v4:
patch moved to after 'drm/i915/psr: Avoid PSR exit max time timeout'
to avoid touch in 2 patches EDP_PSR_DEBUG.

v3:
disabling PSR instead of exiting on error

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180626201644.21932-5-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index caad19f5f557fd9c79304a922aa22b54a92bf96c..43db91c19f52412e1b01dbaf1dbd72f33554450a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4044,6 +4044,7 @@ enum {
 #define   EDP_PSR_SKIP_AUX_EXIT                        (1 << 12)
 #define   EDP_PSR_TP1_TP2_SEL                  (0 << 11)
 #define   EDP_PSR_TP1_TP3_SEL                  (1 << 11)
+#define   EDP_PSR_CRC_ENABLE                   (1 << 10) /* BDW+ */
 #define   EDP_PSR_TP2_TP3_TIME_500us           (0 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_100us           (1 << 8)
 #define   EDP_PSR_TP2_TP3_TIME_2500us          (2 << 8)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index aa98b62910b40cc940fbe888d8e9482c29eee9bd..45f1cb7d6c0435c6e580626138b319a2e248fbba 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -323,6 +323,8 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 
        if (dev_priv->psr.link_standby)
                dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
+       if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
+               dpcd_val |= DP_PSR_CRC_VERIFICATION;
        drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 
        drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
@@ -378,6 +380,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
        else
                val |= EDP_PSR_TP1_TP2_SEL;
 
+       if (INTEL_GEN(dev_priv) >= 8)
+               val |= EDP_PSR_CRC_ENABLE;
+
        val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
        I915_WRITE(EDP_PSR_CTL, val);
 }
@@ -951,7 +956,8 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
        struct i915_psr *psr = &dev_priv->psr;
        u8 val;
        const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
-                         DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR;
+                         DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
+                         DP_PSR_LINK_CRC_ERROR;
 
        if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))
                return;
@@ -980,6 +986,8 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
                DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");
        if (val & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
                DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");
+       if (val & DP_PSR_LINK_CRC_ERROR)
+               DRM_ERROR("PSR Link CRC error, disabling PSR\n");
 
        if (val & ~errors)
                DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",