drm/amd/display: Add Azalia registers to HW sequencer

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 057407892618463a999082ca2bde82b8ab69520d..f091d87f8f8bc3b428159474f4a45e11d3f3c0c8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -275,6 +275,8 @@ struct dce_hwseq_registers {
        uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;
        uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR;
        uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR;
+       uint32_t AZALIA_AUDIO_DTO;
+       uint32_t AZALIA_CONTROLLER_CLOCK_GATING;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -500,7 +502,8 @@ struct dce_hwseq_registers {
        type D1VGA_MODE_ENABLE; \
        type D2VGA_MODE_ENABLE; \
        type D3VGA_MODE_ENABLE; \
-       type D4VGA_MODE_ENABLE;
+       type D4VGA_MODE_ENABLE; \
+       type AZALIA_AUDIO_DTO_MODULE;
 
 struct dce_hwseq_shift {
        HWSEQ_REG_FIELD_LIST(uint8_t)