KVM: arm/arm64: vgic: Get rid of MISR and EISR fields
authorChristoffer Dall <christoffer.dall@linaro.org>
Thu, 29 Dec 2016 14:57:31 +0000 (15:57 +0100)
committerChristoffer Dall <cdall@linaro.org>
Sun, 9 Apr 2017 14:49:10 +0000 (07:49 -0700)
We don't use these fields anymore so let's nuke them completely.

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
include/kvm/arm_vgic.h
virt/kvm/arm/hyp/vgic-v2-sr.c
virt/kvm/arm/hyp/vgic-v3-sr.c

index ea940dbb5dba7ec87449ff40b4fd0ab6080e338b..26ed4fb896bb4826919d7fb581d19941f9d7d1e3 100644 (file)
@@ -225,8 +225,6 @@ struct vgic_dist {
 struct vgic_v2_cpu_if {
        u32             vgic_hcr;
        u32             vgic_vmcr;
-       u32             vgic_misr;      /* Saved only */
-       u64             vgic_eisr;      /* Saved only */
        u64             vgic_elrsr;     /* Saved only */
        u32             vgic_apr;
        u32             vgic_lr[VGIC_V2_MAX_LRS];
@@ -236,8 +234,6 @@ struct vgic_v3_cpu_if {
        u32             vgic_hcr;
        u32             vgic_vmcr;
        u32             vgic_sre;       /* Restored only, change ignored */
-       u32             vgic_misr;      /* Saved only */
-       u32             vgic_eisr;      /* Saved only */
        u32             vgic_elrsr;     /* Saved only */
        u32             vgic_ap0r[4];
        u32             vgic_ap1r[4];
index a4c3bb00572587aaa963fb1c0b9ac59d57ab57c9..a3f18d3623661ae6204750fa9aa8639a5fde7617 100644 (file)
@@ -77,9 +77,7 @@ void __hyp_text __vgic_v2_save_state(struct kvm_vcpu *vcpu)
 
                writel_relaxed(0, base + GICH_HCR);
        } else {
-               cpu_if->vgic_eisr = 0;
                cpu_if->vgic_elrsr = ~0UL;
-               cpu_if->vgic_misr = 0;
                cpu_if->vgic_apr = 0;
        }
 }
index 41bbbb054a6fa303f278610984299eaf52d32cd5..3d0b1ddb69298261e87fd7dc034d6dbd188a39df 100644 (file)
@@ -170,8 +170,6 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
                        cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
                }
        } else {
-               cpu_if->vgic_misr  = 0;
-               cpu_if->vgic_eisr  = 0;
                cpu_if->vgic_elrsr = 0xffff;
                cpu_if->vgic_ap0r[0] = 0;
                cpu_if->vgic_ap0r[1] = 0;