This allows us to later define a callback for both.
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
struct ath_common *common = ath9k_hw_common(ah);
struct ieee80211_channel *channel = chan->chan;
u32 synthDelay, qnum;
+ int r;
for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
if (ath9k_hw_numtxpending(ah, qnum)) {
ath9k_hw_set_regs(ah, chan);
- if (AR_SREV_9280_10_OR_LATER(ah)) {
- ath9k_hw_ar9280_set_channel(ah, chan);
- } else {
- if (!(ath9k_hw_set_channel(ah, chan))) {
- ath_print(common, ATH_DBG_FATAL,
- "Failed to set channel\n");
- return false;
- }
+ if (AR_SREV_9280_10_OR_LATER(ah))
+ r = ath9k_hw_ar9280_set_channel(ah, chan);
+ else
+ r = ath9k_hw_set_channel(ah, chan);
+ if (r) {
+ ath_print(common, ATH_DBG_FATAL,
+ "Failed to set channel\n");
+ return false;
}
ah->eep_ops->set_txpower(ah, chan,
REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
if (AR_SREV_9280_10_OR_LATER(ah))
- ath9k_hw_ar9280_set_channel(ah, chan);
+ r = ath9k_hw_ar9280_set_channel(ah, chan);
else
- if (!(ath9k_hw_set_channel(ah, chan)))
- return -EIO;
+ r = ath9k_hw_set_channel(ah, chan);
+ if (r)
+ return r;
for (i = 0; i < AR_NUM_DCU; i++)
REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
* the channel value. Assumes writes enabled to analog bus and bank6 register
* cache in ah->analogBank6Data.
*/
-bool
-ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
+int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
{
struct ath_common *common = ath9k_hw_common(ah);
u32 channelSel = 0;
} else {
ath_print(common, ATH_DBG_FATAL,
"Invalid channel %u MHz\n", freq);
- return false;
+ return -EINVAL;
}
channelSel = (channelSel << 2) & 0xff;
} else {
ath_print(common, ATH_DBG_FATAL,
"Invalid channel %u MHz\n", freq);
- return false;
+ return -EINVAL;
}
reg32 =
ah->curchan = chan;
ah->curchan_rad_index = -1;
- return true;
+ return 0;
}
/**
* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
* (freq_ref = 40MHz/(24>>amodeRefSel))
*/
-void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
- struct ath9k_channel *chan)
+int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
{
u16 bMode, fracMode, aModeRefSel = 0;
u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
ah->curchan = chan;
ah->curchan_rad_index = -1;
+
+ return 0;
}
/**
#ifndef PHY_H
#define PHY_H
-void ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
- struct ath9k_channel
- *chan);
-bool ath9k_hw_set_channel(struct ath_hw *ah,
- struct ath9k_channel *chan);
+int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
+int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex,
u32 freqIndex, int regWrites);
bool ath9k_hw_set_rf_regs(struct ath_hw *ah,