clk: tegra124: init table updates

Ensure some clocks critical for system operation are always. Also enable csite
for JTAG debugging and set the tsensor and soc_therm clock frequencies for the
upcoming soctherm driver.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 61064247274692c38bced7954b0eb075209837db..9525c684d14930267fbf00ec634550e52469a373 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1371,6 +1371,12 @@ static struct tegra_clk_init_table init_table[] __initdata = {
        {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
        {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
        {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
+       {TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1},
+       {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
+       {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
+       {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
+       {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
+       {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
        /* This MUST be the last entry. */
        {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
 };