qed*: Refactor mf_mode to consist of bits.
authorSudarsana Reddy Kalluru <sudarsana.kalluru@cavium.com>
Sun, 6 May 2018 01:42:59 +0000 (18:42 -0700)
committerDavid S. Miller <davem@davemloft.net>
Tue, 8 May 2018 03:46:10 +0000 (23:46 -0400)
`mf_mode' field indicates the multi-partitioning mode the device is
configured to. This method doesn't scale very well, adding a new MF mode
requires going over all the existing conditions, and deciding whether those
are needed for the new mode or not.
The patch defines a set of bit-fields for modes which are derived according
to the mode info shared by the MFW and all the configuration would be made
according to those. To add a new mode, there would be a single place where
we'll need to go and choose which bits apply and which don't.

Signed-off-by: Sudarsana Reddy Kalluru <Sudarsana.Kalluru@cavium.com>
Signed-off-by: Ariel Elior <ariel.elior@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/qlogic/qed/qed.h
drivers/net/ethernet/qlogic/qed/qed_dev.c
drivers/net/ethernet/qlogic/qed/qed_ll2.c
drivers/net/ethernet/qlogic/qed/qed_main.c
drivers/net/ethernet/qlogic/qed/qed_sp.h
drivers/net/ethernet/qlogic/qed/qed_sp_commands.c
drivers/net/ethernet/qlogic/qede/qede_main.c
include/linux/qed/qed_if.h

index e07460a68d303267e9f45ab48f875855cee4bdcd..c8f3507d1151503bd4d464cf0933c4f1d3835a9f 100644 (file)
@@ -439,6 +439,41 @@ struct qed_fw_data {
        u32                     init_ops_size;
 };
 
+enum qed_mf_mode_bit {
+       /* Supports PF-classification based on tag */
+       QED_MF_OVLAN_CLSS,
+
+       /* Supports PF-classification based on MAC */
+       QED_MF_LLH_MAC_CLSS,
+
+       /* Supports PF-classification based on protocol type */
+       QED_MF_LLH_PROTO_CLSS,
+
+       /* Requires a default PF to be set */
+       QED_MF_NEED_DEF_PF,
+
+       /* Allow LL2 to multicast/broadcast */
+       QED_MF_LL2_NON_UNICAST,
+
+       /* Allow Cross-PF [& child VFs] Tx-switching */
+       QED_MF_INTER_PF_SWITCH,
+
+       /* Unified Fabtic Port support enabled */
+       QED_MF_UFP_SPECIFIC,
+
+       /* Disable Accelerated Receive Flow Steering (aRFS) */
+       QED_MF_DISABLE_ARFS,
+
+       /* Use vlan for steering */
+       QED_MF_8021Q_TAGGING,
+
+       /* Use stag for steering */
+       QED_MF_8021AD_TAGGING,
+
+       /* Allow DSCP to TC mapping */
+       QED_MF_DSCP_TO_TC_MAP,
+};
+
 enum BAR_ID {
        BAR_ID_0,               /* used for GRC */
        BAR_ID_1                /* Used for doorbells */
@@ -669,10 +704,8 @@ struct qed_dev {
        u8                              num_funcs_in_port;
 
        u8                              path_id;
-       enum qed_mf_mode                mf_mode;
-#define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
-#define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
-#define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
+
+       unsigned long                   mf_bits;
 
        int                             pcie_width;
        int                             pcie_speed;
index d2ad5e92c74f57a7d1fcd2f50ff296ba849071cd..9b07d7f25042e0125a36d6c320f7d51bb911b9ac 100644 (file)
@@ -1149,18 +1149,10 @@ static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
                return -EINVAL;
        }
 
-       switch (p_hwfn->cdev->mf_mode) {
-       case QED_MF_DEFAULT:
-       case QED_MF_NPAR:
-               hw_mode |= 1 << MODE_MF_SI;
-               break;
-       case QED_MF_OVLAN:
+       if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
                hw_mode |= 1 << MODE_MF_SD;
-               break;
-       default:
-               DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
+       else
                hw_mode |= 1 << MODE_MF_SI;
-       }
 
        hw_mode |= 1 << MODE_ASIC;
 
@@ -1557,7 +1549,6 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
 
                /* send function start command */
                rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
-                                    p_hwfn->cdev->mf_mode,
                                     allow_npar_tx_switch);
                if (rc) {
                        DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
@@ -2651,17 +2642,25 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 
        switch (mf_mode) {
        case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
-               p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
+               p_hwfn->cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
                break;
        case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
-               p_hwfn->cdev->mf_mode = QED_MF_NPAR;
+               p_hwfn->cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
+                                       BIT(QED_MF_LLH_PROTO_CLSS) |
+                                       BIT(QED_MF_LL2_NON_UNICAST) |
+                                       BIT(QED_MF_INTER_PF_SWITCH);
                break;
        case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
-               p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
+               p_hwfn->cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
+                                       BIT(QED_MF_LLH_PROTO_CLSS) |
+                                       BIT(QED_MF_LL2_NON_UNICAST);
+               if (QED_IS_BB(p_hwfn->cdev))
+                       p_hwfn->cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
                break;
        }
-       DP_INFO(p_hwfn, "Multi function mode is %08x\n",
-               p_hwfn->cdev->mf_mode);
+
+       DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
+               p_hwfn->cdev->mf_bits);
 
        /* Read Multi-function information from shmem */
        addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
@@ -3462,7 +3461,7 @@ int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
        u32 high = 0, low = 0, en;
        int i;
 
-       if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
+       if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
                return 0;
 
        qed_llh_mac_to_filter(&high, &low, p_filter);
@@ -3507,7 +3506,7 @@ void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
        u32 high = 0, low = 0;
        int i;
 
-       if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
+       if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
                return;
 
        qed_llh_mac_to_filter(&high, &low, p_filter);
@@ -3549,7 +3548,7 @@ qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
        u32 high = 0, low = 0, en;
        int i;
 
-       if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
+       if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
                return 0;
 
        switch (type) {
@@ -3647,7 +3646,7 @@ qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
        u32 high = 0, low = 0;
        int i;
 
-       if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
+       if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
                return;
 
        switch (type) {
index 38502815d681d08086f02bbb49e340c06658766d..6c942c133b2c80534a668dbad7e32df25fcc6939 100644 (file)
@@ -922,9 +922,9 @@ static int qed_sp_ll2_rx_queue_start(struct qed_hwfn *p_hwfn,
        p_ramrod->queue_id = p_ll2_conn->queue_id;
        p_ramrod->main_func_queue = p_ll2_conn->main_func_queue ? 1 : 0;
 
-       if ((IS_MF_DEFAULT(p_hwfn) || IS_MF_SI(p_hwfn)) &&
-           p_ramrod->main_func_queue && (conn_type != QED_LL2_TYPE_ROCE) &&
-           (conn_type != QED_LL2_TYPE_IWARP)) {
+       if (test_bit(QED_MF_LL2_NON_UNICAST, &p_hwfn->cdev->mf_bits) &&
+           p_ramrod->main_func_queue && conn_type != QED_LL2_TYPE_ROCE &&
+           conn_type != QED_LL2_TYPE_IWARP) {
                p_ramrod->mf_si_bcast_accept_all = 1;
                p_ramrod->mf_si_mcast_accept_all = 1;
        } else {
index d1d3787affe86d6216c6f64e34cdf7d4d477075f..307fe33d75c8fd6883cb8ecb448454d49a8ba2e0 100644 (file)
@@ -264,7 +264,8 @@ int qed_fill_dev_info(struct qed_dev *cdev,
        dev_info->pci_mem_end = cdev->pci_params.mem_end;
        dev_info->pci_irq = cdev->pci_params.irq;
        dev_info->rdma_supported = QED_IS_RDMA_PERSONALITY(p_hwfn);
-       dev_info->is_mf_default = IS_MF_DEFAULT(&cdev->hwfns[0]);
+       dev_info->is_mf_default = !test_bit(QED_MF_LLH_MAC_CLSS,
+                                           &cdev->mf_bits);
        dev_info->dev_type = cdev->type;
        ether_addr_copy(dev_info->hw_mac, hw_info->hw_mac_addr);
 
@@ -273,7 +274,8 @@ int qed_fill_dev_info(struct qed_dev *cdev,
                dev_info->fw_minor = FW_MINOR_VERSION;
                dev_info->fw_rev = FW_REVISION_VERSION;
                dev_info->fw_eng = FW_ENGINEERING_VERSION;
-               dev_info->mf_mode = cdev->mf_mode;
+               dev_info->b_inter_pf_switch = test_bit(QED_MF_INTER_PF_SWITCH,
+                                                      &cdev->mf_bits);
                dev_info->tx_switching = true;
 
                if (hw_info->b_wol_support == QED_WOL_SUPPORT_PME)
index ab4ad8a1e2a5e3a9e1a846d82341468719073ea1..768022235451b4089619c8a61d69ddc2eb167159 100644 (file)
@@ -416,7 +416,6 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn,
  * @param p_hwfn
  * @param p_ptt
  * @param p_tunn
- * @param mode
  * @param allow_npar_tx_switch
  *
  * @return int
@@ -425,7 +424,7 @@ int qed_sp_init_request(struct qed_hwfn *p_hwfn,
 int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
                    struct qed_ptt *p_ptt,
                    struct qed_tunnel_info *p_tunn,
-                   enum qed_mf_mode mode, bool allow_npar_tx_switch);
+                   bool allow_npar_tx_switch);
 
 /**
  * @brief qed_sp_pf_update - PF Function Update Ramrod
index 5e927b6cac221c187ad37f77d4a5563c83e9bc90..fbb317257629a0238a0b82e1ec34eba2664daaa8 100644 (file)
@@ -306,7 +306,7 @@ qed_tunn_set_pf_start_params(struct qed_hwfn *p_hwfn,
 int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
                    struct qed_ptt *p_ptt,
                    struct qed_tunnel_info *p_tunn,
-                   enum qed_mf_mode mode, bool allow_npar_tx_switch)
+                   bool allow_npar_tx_switch)
 {
        struct pf_start_ramrod_data *p_ramrod = NULL;
        u16 sb = qed_int_get_sp_sb_id(p_hwfn);
@@ -339,18 +339,10 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
        p_ramrod->dont_log_ramrods      = 0;
        p_ramrod->log_type_mask         = cpu_to_le16(0xf);
 
-       switch (mode) {
-       case QED_MF_DEFAULT:
-       case QED_MF_NPAR:
-               p_ramrod->mf_mode = MF_NPAR;
-               break;
-       case QED_MF_OVLAN:
+       if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
                p_ramrod->mf_mode = MF_OVLAN;
-               break;
-       default:
-               DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
+       else
                p_ramrod->mf_mode = MF_NPAR;
-       }
 
        p_ramrod->outer_tag_config.outer_tag.tci =
                cpu_to_le16(p_hwfn->hw_info.ovlan);
@@ -365,7 +357,7 @@ int qed_sp_pf_start(struct qed_hwfn *p_hwfn,
 
        qed_tunn_set_pf_start_params(p_hwfn, p_tunn, &p_ramrod->tunnel_config);
 
-       if (IS_MF_SI(p_hwfn))
+       if (test_bit(QED_MF_INTER_PF_SWITCH, &p_hwfn->cdev->mf_bits))
                p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
 
        switch (p_hwfn->hw_info.personality) {
index a01e7d6e5442f079e9006811b82b4feb02dc23bc..89c581c3c21a9a94485ab6a69d32fb14848929d3 100644 (file)
@@ -199,7 +199,7 @@ static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
 
        /* Enable/Disable Tx switching for PF */
        if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
-           qed_info->mf_mode != QED_MF_NPAR && qed_info->tx_switching) {
+           !qed_info->b_inter_pf_switch && qed_info->tx_switching) {
                vport_params->vport_id = 0;
                vport_params->update_tx_switching_flg = 1;
                vport_params->tx_switching_flg = num_vfs_param ? 1 : 0;
@@ -1928,7 +1928,7 @@ static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
        vport_update_params->update_vport_active_flg = 1;
        vport_update_params->vport_active_flg = 1;
 
-       if ((qed_info->mf_mode == QED_MF_NPAR || pci_num_vf(edev->pdev)) &&
+       if ((qed_info->b_inter_pf_switch || pci_num_vf(edev->pdev)) &&
            qed_info->tx_switching) {
                vport_update_params->update_tx_switching_flg = 1;
                vport_update_params->tx_switching_flg = 1;
index e53f9c7c2809f938b042015e18e47b7d0a1ec2f6..5dac56147a07743503eaa45f970a1d488a9eebea 100644 (file)
@@ -359,7 +359,7 @@ struct qed_dev_info {
 #define QED_MFW_VERSION_3_OFFSET       24
 
        u32             flash_size;
-       u8              mf_mode;
+       bool            b_inter_pf_switch;
        bool            tx_switching;
        bool            rdma_supported;
        u16             mtu;