drm/amd/display: Program v_total_min/max after v_total_cntl

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index be7153924a708049f51d44025923415875685f63..1b2fe0df347f7bf786c10d14bab5639decfacdd8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -431,14 +431,6 @@ void dce110_timing_generator_set_drr(
                        0,
                        CRTC_V_TOTAL_CONTROL,
                        CRTC_SET_V_TOTAL_MIN_MASK);
-               set_reg_field_value(v_total_min,
-                               0,
-                               CRTC_V_TOTAL_MIN,
-                               CRTC_V_TOTAL_MIN);
-               set_reg_field_value(v_total_max,
-                               0,
-                               CRTC_V_TOTAL_MAX,
-                               CRTC_V_TOTAL_MAX);
                set_reg_field_value(v_total_cntl,
                                0,
                                CRTC_V_TOTAL_CONTROL,
@@ -447,6 +439,14 @@ void dce110_timing_generator_set_drr(
                                0,
                                CRTC_V_TOTAL_CONTROL,
                                CRTC_V_TOTAL_MAX_SEL);
+               set_reg_field_value(v_total_min,
+                               0,
+                               CRTC_V_TOTAL_MIN,
+                               CRTC_V_TOTAL_MIN);
+               set_reg_field_value(v_total_max,
+                               0,
+                               CRTC_V_TOTAL_MAX,
+                               CRTC_V_TOTAL_MAX);
                set_reg_field_value(v_total_cntl,
                                0,
                                CRTC_V_TOTAL_CONTROL,

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 7bee78172d8530f12a1ea980eca4e97de08ad9a0..2ea490f8482e04f2951c82ea8b27c9332835bb8f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -570,18 +570,18 @@ void dce120_timing_generator_set_drr(
                                0x180);
 
        } else {
-               CRTC_REG_UPDATE(
-                               CRTC0_CRTC_V_TOTAL_MIN,
-                               CRTC_V_TOTAL_MIN, 0);
-               CRTC_REG_UPDATE(
-                               CRTC0_CRTC_V_TOTAL_MAX,
-                               CRTC_V_TOTAL_MAX, 0);
                CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,
                                FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
                                FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
                                FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
                                FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
                                FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
+               CRTC_REG_UPDATE(
+                               CRTC0_CRTC_V_TOTAL_MIN,
+                               CRTC_V_TOTAL_MIN, 0);
+               CRTC_REG_UPDATE(
+                               CRTC0_CRTC_V_TOTAL_MAX,
+                               CRTC_V_TOTAL_MAX, 0);
                CRTC_REG_UPDATE(
                                CRTC0_CRTC_STATIC_SCREEN_CONTROL,
                                CRTC_STATIC_SCREEN_EVENT_MASK,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index f56eac0e4dd20e19ef2f0b993bf181441a3e4f62..dc921307874aac614ddaf51e511abf8a69dbf933 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -855,17 +855,17 @@ void optc1_set_drr(
                                OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
                                OTG_SET_V_TOTAL_MIN_MASK, 0);
        } else {
-               REG_SET(OTG_V_TOTAL_MIN, 0,
-                       OTG_V_TOTAL_MIN, 0);
-
-               REG_SET(OTG_V_TOTAL_MAX, 0,
-                       OTG_V_TOTAL_MAX, 0);
-
                REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
                                OTG_SET_V_TOTAL_MIN_MASK, 0,
                                OTG_V_TOTAL_MIN_SEL, 0,
                                OTG_V_TOTAL_MAX_SEL, 0,
                                OTG_FORCE_LOCK_ON_EVENT, 0);
+
+               REG_SET(OTG_V_TOTAL_MIN, 0,
+                       OTG_V_TOTAL_MIN, 0);
+
+               REG_SET(OTG_V_TOTAL_MAX, 0,
+                       OTG_V_TOTAL_MAX, 0);
        }
 }