PCI/ASPM: Add L1 substate capability structure register definitions

Add L1 substate capability structure register definitions for use in
subsequent patches.  See the PCIe r3.1 spec, sec 7.33.

[bhelgaas: add PCIe spec reference]
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 174d1147081bccf618e851a85e20ff79895bfd00..f48d06e2bb4dbcacc2cb725f5cedd5aa6feb0d54 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -682,6 +682,7 @@
 #define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
 #define PCI_EXT_CAP_ID_PASID   0x1B    /* Process Address Space ID */
 #define PCI_EXT_CAP_ID_DPC     0x1D    /* Downstream Port Containment */
+#define PCI_EXT_CAP_ID_L1SS    0x1E    /* L1 PM Substates */
 #define PCI_EXT_CAP_ID_PTM     0x1F    /* Precision Time Measurement */
 #define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_PTM
 
@@ -985,4 +986,19 @@
 #define  PCI_PTM_CTRL_ENABLE           0x00000001  /* PTM enable */
 #define  PCI_PTM_CTRL_ROOT             0x00000002  /* Root select */
 
+/* L1 PM Substates */
+#define PCI_L1SS_CAP               4   /* capability register */
+#define  PCI_L1SS_CAP_PCIPM_L1_2        1      /* PCI PM L1.2 Support */
+#define  PCI_L1SS_CAP_PCIPM_L1_1        2      /* PCI PM L1.1 Support */
+#define  PCI_L1SS_CAP_ASPM_L1_2                 4      /* ASPM L1.2 Support */
+#define  PCI_L1SS_CAP_ASPM_L1_1                 8      /* ASPM L1.1 Support */
+#define  PCI_L1SS_CAP_L1_PM_SS         16      /* L1 PM Substates Support */
+#define PCI_L1SS_CTL1              8   /* Control Register 1 */
+#define  PCI_L1SS_CTL1_PCIPM_L1_2      1       /* PCI PM L1.2 Enable */
+#define  PCI_L1SS_CTL1_PCIPM_L1_1      2       /* PCI PM L1.1 Support */
+#define  PCI_L1SS_CTL1_ASPM_L1_2       4       /* ASPM L1.2 Support */
+#define  PCI_L1SS_CTL1_ASPM_L1_1       8       /* ASPM L1.1 Support */
+#define  PCI_L1SS_CTL1_L1SS_MASK       0x0000000F
+#define PCI_L1SS_CTL2              0xC /* Control Register 2 */
+
 #endif /* LINUX_PCI_REGS_H */