ARM i.MX5: set CAN peripheral clock to 24 MHz parent

This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.

In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index e349fd5aab9bbd9d18da630c591198be7da6f12d..dff5ca921d001f128df9c27621a626c1e4b02aa0 100644 (file)
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -584,6 +584,9 @@ static void __init mx53_clocks_init(struct device_node *np)
        clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
        clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
 
+       /* move can bus clk to 24MHz */
+       clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
+
        clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
        imx_print_silicon_rev("i.MX53", mx53_revision());
        clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);