MIPS: Add P6600 cases to CPU switch statements

Add cases supporting the P6600 CPU to various switch statements in
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Petri Gynther <pgynther@google.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12343/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index abee2bfd10dc1dce791ae5691417303d58b08ce6..2cb0979b5dc5a0bc36b46468f433a2f92bd7ea35 100644 (file)
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -79,6 +79,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
        case CPU_I6400:
+       case CPU_P6600:
 #endif
 
 #ifdef CONFIG_SYS_HAS_CPU_R3000

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e0cfa3b85bca4cc317b25af382debad9dc86f3fc..388503867657fe70bc8059bf45cbf84ab6226da5 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -539,6 +539,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
        switch (c->cputype) {
        case CPU_PROAPTIV:
        case CPU_P5600:
+       case CPU_P6600:
                /* proAptiv & related cores use Config6 to enable the FTLB */
                config = read_c0_config6();
                /* Clear the old probability value */

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 9bc1191b1ab0d32c05d7f7d15e2a6e4995262933..656769c166fc5354c4fe815ded21cd1c15f53853 100644 (file)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1556,6 +1556,7 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
 #endif
                break;
        case CPU_P5600:
+       case CPU_P6600:
        case CPU_I6400:
                /* 8-bit event numbers */
                raw_id = config & 0x1ff;
@@ -1718,6 +1719,11 @@ init_hw_perf_events(void)
                mipspmu.general_event_map = &mipsxxcore_event_map2;
                mipspmu.cache_event_map = &mipsxxcore_cache_map2;
                break;
+       case CPU_P6600:
+               mipspmu.name = "mips/P6600";
+               mipspmu.general_event_map = &mipsxxcore_event_map2;
+               mipspmu.cache_event_map = &mipsxxcore_cache_map2;
+               break;
        case CPU_I6400:
                mipspmu.name = "mips/I6400";
                mipspmu.general_event_map = &mipsxxcore_event_map2;

diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
index 8489c88f9932310b7732e1ec396ca2fb2000078c..d6e6cf75114d633f89b0b81a352a6fac052e99de 100644 (file)
--- a/arch/mips/kernel/spram.c
+++ b/arch/mips/kernel/spram.c
@@ -210,6 +210,7 @@ void spram_config(void)
        case CPU_P5600:
        case CPU_QEMU_GENERIC:
        case CPU_I6400:
+       case CPU_P6600:
                config0 = read_c0_config();
                /* FIXME: addresses are Malta specific */
                if (config0 & (1<<24)) {

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index bd4893feffa6d50672ab19b20c8406956f99315f..4358f025b752810113588e1bc305126ca6fd1732 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1644,6 +1644,7 @@ static inline void parity_protection_init(void)
        case CPU_P5600:
        case CPU_QEMU_GENERIC:
        case CPU_I6400:
+       case CPU_P6600:
                {
 #define ERRCTL_PE      0x80000000
 #define ERRCTL_L2P     0x00800000

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 69e7e5873af37d7bdc892f21a69a78fb23105477..729a7d48ceee8ade9016f4d43c3ab111e119d292 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1285,6 +1285,7 @@ static void probe_pcache(void)
        case CPU_M5150:
        case CPU_QEMU_GENERIC:
        case CPU_I6400:
+       case CPU_P6600:
                if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
                    (c->icache.waysize > PAGE_SIZE))
                        c->icache.flags |= MIPS_CACHE_ALIASES;

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 91dec32c77b722a838ce9ca352d89ca3939fba2b..286a4d5a18843c82be783dfde6b12798d191869e 100644 (file)
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -141,6 +141,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
        case CPU_P5600:
        case CPU_BMIPS5000:
        case CPU_QEMU_GENERIC:
+       case CPU_P6600:
                if (config2 & (1 << 12))
                        return 0;
        }