drm/i915: Use the "display core" power domain in vlv/chv set_cdclk()

The PFI credit programming performed during cdclk change on vlv/chv
requires access to a register in the disp2d power well. So far
we've abused pipe-A power domain for this, but now we have the
more appropriate "display core" domain so let's make use of it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190701161534.6671-1-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0b8b8ae3b7fca1fee1ee2e5d36af64e941219f38..d0581a1ac2431f8e3ebf258569bba401ddc58802 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -545,10 +545,10 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
        /* There are cases where we can end up here with power domains
         * off and a CDCLK frequency other than the minimum, like when
         * issuing a modeset without actually changing any display after
-        * a system suspend.  So grab the PIPE-A domain, which covers
+        * a system suspend.  So grab the display core domain, which covers
         * the HW blocks needed for the following programming.
         */
-       wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+       wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 
        vlv_iosf_sb_get(dev_priv,
                        BIT(VLV_IOSF_SB_CCK) |
@@ -606,7 +606,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 
        vlv_program_pfi_credits(dev_priv);
 
-       intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
+       intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 }
 
 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
@@ -631,10 +631,10 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
        /* There are cases where we can end up here with power domains
         * off and a CDCLK frequency other than the minimum, like when
         * issuing a modeset without actually changing any display after
-        * a system suspend.  So grab the PIPE-A domain, which covers
+        * a system suspend.  So grab the display core domain, which covers
         * the HW blocks needed for the following programming.
         */
-       wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+       wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 
        vlv_punit_get(dev_priv);
        val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
@@ -653,7 +653,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 
        vlv_program_pfi_credits(dev_priv);
 
-       intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);
+       intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 }
 
 static int bdw_calc_cdclk(int min_cdclk)