drm/i915/icl: Define T_INIT_MASTER registers

This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1531215614-6828-5-git-send-email-madhav.chauhan@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09bc8e730ee1260553ecdf30a0ed170f6e3fc968..c80e56959e21b88a6f9fdb034315eba9fd8efce7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10231,6 +10231,12 @@ enum skl_power_gate {
 #define  PREPARE_COUNT_SHIFT                           0
 #define  PREPARE_COUNT_MASK                            (0x3f << 0)
 
+#define _ICL_DSI_T_INIT_MASTER_0       0x6b088
+#define _ICL_DSI_T_INIT_MASTER_1       0x6b888
+#define ICL_DSI_T_INIT_MASTER(port)    _MMIO_PORT(port,        \
+                                                  _ICL_DSI_T_INIT_MASTER_0,\
+                                                  _ICL_DSI_T_INIT_MASTER_1)
+
 /* bits 31:0 */
 #define _MIPIA_DBI_BW_CTRL             (dev_priv->mipi_mmio_base + 0xb084)
 #define _MIPIC_DBI_BW_CTRL             (dev_priv->mipi_mmio_base + 0xb884)