drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for ST

Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7e94a85daef507cc4decb8f2522dabc49612c89f..b15162dc14eaa8977c1f081824279c8037d066c3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4292,7 +4292,8 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
        WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
 
        data = RREG32(mmRLC_SERDES_WR_CTRL);
-       data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
+       if (adev->asic_type == CHIP_STONEY)
+                       data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
                        RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
                        RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
                        RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
@@ -4300,13 +4301,23 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
                        RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
                        RLC_SERDES_WR_CTRL__POWER_UP_MASK |
                        RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
-                       RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
-                       RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
                        RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
+       else
+               data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
+                         RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
+                         RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
+                         RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
+                         RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
+                         RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
+                         RLC_SERDES_WR_CTRL__POWER_UP_MASK |
+                         RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
+                         RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
+                         RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
+                         RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
        data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
-                       (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
-                       (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
-                       (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
+                (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
+                (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
+                (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
 
        WREG32(mmRLC_SERDES_WR_CTRL, data);
 }