drm/amd/display: Refine update flags usage in update_dchubp_dpp

- Only update DPP clock if it's a full update.
- Program viewport on position change. This caused SLS regressions.

Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e9ecbcb66e80cd98dc87f7eea6ebed30305fd3b7..7846534cd6d548c64e34588bd3a7271890850427 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1726,7 +1726,7 @@ static void update_dchubp_dpp(
        union plane_size size = plane_state->plane_size;
 
        /* depends on DML calculation, DPP clock value may change dynamically */
-       if (pipe_ctx->plane_state->update_flags.raw != 0) {
+       if (plane_state->update_flags.bits.full_update) {
                enable_dppclk(
                        dc->hwseq,
                        pipe_ctx->pipe_idx,
@@ -1770,7 +1770,8 @@ static void update_dchubp_dpp(
        }
 
        if (plane_state->update_flags.bits.full_update ||
-               plane_state->update_flags.bits.scaling_change) {
+               plane_state->update_flags.bits.scaling_change ||
+               plane_state->update_flags.bits.position_change) {
                hubp->funcs->mem_program_viewport(
                        hubp,
                        &pipe_ctx->plane_res.scl_data.viewport,